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Cypress Semiconductor /psoc63 /FLASHC /CM0_CA_CTL1

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Interpret as CM0_CA_CTL1

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31282724232019161512118743000000000000000000000000000000000000000000 (OFF)PWR_MODE0VECTKEYSTAT

PWR_MODE=OFF

Description

CM0+ cache control

Fields

PWR_MODE

Set Power mode for CM0 cache

0 (OFF): See CM4_PWR_CTL

1 (RSVD): undefined

2 (RETAINED): See CM4_PWR_CTL

3 (ENABLED): See CM4_PWR_CTL
VECTKEYSTAT

Register key (to prevent accidental writes).

  • Should be written with a 0x05fa key value for the write to take effect.
  • Always reads as 0xfa05.

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data